The present invention relates to a semiconductor memory device and a data transmission method thereof, and more particularly to a semiconductor memory device capable of a high speed transmission of data in a row unit or in (1/n)-row unit data and a data transmission method thereof.
Recently, the requirements for improvement in high speed operation of a large capacity main memory and for a response to increasing high frequency have been on the increase. Notwithstanding, it seems difficult to further more improve the high speed performance of the conventional dynamic random access memory used as a main memory. It was proposed to mount a high speed memory in the main memory, so that the high speed memory performs high speed data transmissions to external device whilst the dynamic random access memory serves to provide a large memory capacity. Namely, the main memory has a multi-level structure responsible for not only the large memory capacity but also the high speed performance.
Operational cycle of the dynamic random access memory is slower than operational cycle of the high speed memory in the dynamic random access memory. It is necessary to increase the number of bits for data transmissions between the high speed memory and the dynamic random access memory, so that a large amount of data transmission between the high speed memory and the dynamic random access memory can be realized and also a gap or a difference in operational speed between the high speed memory and the dynamic random access memory can be compensated,
Further, the high speed memory is much smaller in memory capacity than the dynamic random access memory, for which reason effective use of the high speed memory needs to allow data transmissions between the high speed memory and the dynamic random access memory.
In order to achieve the above requirement, it is necessary to inter-connect a large number of sense amplifiers of the dynamic random access memory to a large number of the high speed memories, for which reason a total length of the inter-connections between the sense amplifiers and the high speed memories is so long. The increase in the length of the inter-connections causes an increase in parasitic capacitance of the interconnections. This increase in parasitic capacitance of the interconnections requires increasing driving ability to the high speed memories for data transmissions from the high speed memories to memory cells of the dynamic random access memory through bit lines. The increase in parasitic capacitance of the interconnections makes it necessary to take a longer data transmission time.
Thus, data having been transmitted from the high speed memories are amplified by sense amplifiers of the dynamic random access memory so that amplified data are written into memory cells of the dynamic random access memory. For this purpose, it is necessary that bit lines of the dynamic random access memory are subjected to balance/pre-charge prior to the data transmission, or necessary to inhibit previous amplification to the bit lines by the sense amplifiers.
In the above circumstances, it had been required to develop a novel semiconductor memory device and a data transmission method free from the above problem.